                                                                     
                                                                     
                                                                     
                                             
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;

ENTITY fc_toSpeed IS
  PORT( 
  clk : IN STD_LOGIC;
  clr : IN STD_LOGIC;
  rst : IN STD_LOGIC;
  start : IN STD_LOGIC;
  ready_2 : OUT STD_LOGIC;
  speedOut : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
  timeIn : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
  conv_time : OUT std_logic
  );
END ENTITY fc_toSpeed;



ARCHITECTURE v OF fc_toSpeed IS
SIGNAL timeReg: STD_LOGIC_VECTOR(63 DOWNTO 0);
CONSTANT r_dist : real := 21545;
SIGNAL r_speed: real;
SIGNAL r_time : real;


BEGIN
conv_time <= '0';
  PROCESS (clk, rst) BEGIN
    IF rising_edge(clk) THEN
      IF clr = '1' THEN
        speedOut <= (OTHERS => '0');
        start<= '0';
      ELSIF start = '1' THEN
        r_time := real(integer(timeIn));
        r_speed := r_dist/ r_time;
        r_speed := r_speed * 360;
        
        speedOut <= CONV_STD_LOGIC_VECTOR( INTEGER( r_speed), 64 ); 
        ready_2<= '1';
      ELSE
        ready_2<='0';
      END IF;
      ELSIF rst ='1' THEN
        speedOut <= (OTHERS => '0');
        start<= '0';
      END IF;
    END PROCESS;
    
  END ARCHITECTURE v;
